| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_vce_v2_0.c | 50 WREG32(VCE_CLOCK_GATING_B, tmp);
54 WREG32(VCE_UENC_CLOCK_GATING, tmp);
58 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
60 WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
65 WREG32(VCE_CLOCK_GATING_B, tmp);
70 WREG32(VCE_UENC_CLOCK_GATING, tmp);
74 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
90 WREG32(VCE_CLOCK_GATING_B, tmp);
96 WREG32(VCE_UENC_CLOCK_GATING, tmp);
101 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp)
[all...] |
| radeon_rv515.c | 158 WREG32(R_000300_VGA_RENDER_CONTROL,
223 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
225 WREG32(MC_IND_INDEX, 0);
236 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
237 WREG32(MC_IND_DATA, (v));
238 WREG32(MC_IND_INDEX, 0);
312 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
321 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
323 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
324 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0)
[all...] |
| radeon_uvd_v4_2.c | 57 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
58 WREG32(UVD_VCPU_CACHE_SIZE0, size);
62 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
63 WREG32(UVD_VCPU_CACHE_SIZE1, size);
68 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
69 WREG32(UVD_VCPU_CACHE_SIZE2, size);
73 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
77 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1U << 31));
80 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);
|
| radeon_bios.c | 337 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
340 WREG32(AVIVO_D1VGA_CONTROL,
343 WREG32(AVIVO_D2VGA_CONTROL,
346 WREG32(AVIVO_VGA_RENDER_CONTROL,
349 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
354 WREG32(R600_BUS_CNTL, bus_cntl);
356 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
357 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
358 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
360 WREG32(R600_ROM_CNTL, rom_cntl)
[all...] |
| radeon_uvd_v1_0.c | 75 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
128 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
129 WREG32(UVD_VCPU_CACHE_SIZE0, size);
133 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
134 WREG32(UVD_VCPU_CACHE_SIZE1, size);
139 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
140 WREG32(UVD_VCPU_CACHE_SIZE2, size);
144 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
148 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1U << 31));
150 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr))
[all...] |
| radeon_vce_v1_0.c | 102 WREG32(VCE_RB_WPTR, ring->wptr);
104 WREG32(VCE_RB_WPTR2, ring->wptr);
114 WREG32(VCE_CLOCK_GATING_A, tmp);
119 WREG32(VCE_UENC_CLOCK_GATING, tmp);
123 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
127 WREG32(VCE_CLOCK_GATING_A, tmp);
132 WREG32(VCE_UENC_CLOCK_GATING, tmp);
136 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
146 WREG32(VCE_CLOCK_GATING_A, tmp);
151 WREG32(VCE_CLOCK_GATING_B, tmp)
[all...] |
| radeon_dp_auxch.c | 106 WREG32(chan->rec.mask_clk_reg, tmp);
115 WREG32(AUX_CONTROL + aux_offset[instance], tmp);
118 WREG32(AUX_SW_CONTROL + aux_offset[instance],
120 WREG32(AUX_SW_CONTROL + aux_offset[instance],
126 WREG32(AUX_SW_DATA + aux_offset[instance],
130 WREG32(AUX_SW_DATA + aux_offset[instance],
134 WREG32(AUX_SW_DATA + aux_offset[instance],
138 WREG32(AUX_SW_DATA + aux_offset[instance],
144 WREG32(AUX_SW_DATA + aux_offset[instance],
150 WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK)
[all...] |
| radeon_evergreen_hdmi.c | 69 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
85 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
88 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
92 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
93 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
95 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
96 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
98 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
99 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
218 WREG32(AFMT_AVI_INFO0 + offset
[all...] |
| radeon_i2c.c | 127 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
130 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
141 WREG32(rec->mask_clk_reg, temp);
146 WREG32(rec->a_clk_reg, temp);
149 WREG32(rec->a_data_reg, temp);
153 WREG32(rec->en_clk_reg, temp);
156 WREG32(rec->en_data_reg, temp);
160 WREG32(rec->mask_clk_reg, temp);
164 WREG32(rec->mask_data_reg, temp);
179 WREG32(rec->mask_clk_reg, temp)
[all...] |
| radeon_cursor.c | 49 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
56 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
63 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
104 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
106 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
108 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
109 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
115 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH,
118 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH,
122 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset
[all...] |
| radeon_r600.c | 133 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
144 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
145 WREG32(R600_RCU_DATA, (v));
155 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
166 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
167 WREG32(R600_UVD_CTX_DATA, (v));
353 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
880 WREG32(DC_HPD1_INT_CONTROL, tmp);
888 WREG32(DC_HPD2_INT_CONTROL, tmp);
896 WREG32(DC_HPD3_INT_CONTROL, tmp)
[all...] |
| radeon_rv770.c | 821 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
824 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
827 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
828 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
830 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
831 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
833 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
835 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
848 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
915 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vce_v2_0.c | 99 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
101 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
149 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
160 WREG32(mmVCE_CLOCK_GATING_A, tmp);
165 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
170 WREG32(mmVCE_CLOCK_GATING_B, tmp);
180 WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
182 WREG32(mmVCE_LMI_CTRL, 0x00398000);
184 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
185 WREG32(mmVCE_LMI_SWAP_CNTL1, 0)
[all...] |
| amdgpu_gmc_v6_0.c | 89 WREG32(mmBIF_FB_EN, 0);
93 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
107 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
111 WREG32(mmBIF_FB_EN, tmp);
195 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
196 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
200 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
201 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
205 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
209 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008)
[all...] |
| amdgpu_amdkfd_arcturus.c | 146 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
161 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
166 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
167 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
169 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
172 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
174 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
176 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
179 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
181 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI
[all...] |
| amdgpu_cik_ih.c | 72 WREG32(mmIH_CNTL, ih_cntl);
73 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
91 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
92 WREG32(mmIH_CNTL, ih_cntl);
94 WREG32(mmIH_RB_RPTR, 0);
95 WREG32(mmIH_RB_WPTR, 0);
121 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
129 WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
131 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
141 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr))
[all...] |
| amdgpu_si_ih.c | 45 WREG32(IH_CNTL, ih_cntl);
46 WREG32(IH_RB_CNTL, ih_rb_cntl);
57 WREG32(IH_RB_CNTL, ih_rb_cntl);
58 WREG32(IH_CNTL, ih_cntl);
59 WREG32(IH_RB_RPTR, 0);
60 WREG32(IH_RB_WPTR, 0);
73 WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
77 WREG32(INTERRUPT_CNTL, interrupt_cntl);
79 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
87 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr))
[all...] |
| amdgpu_gmc_v8_0.c | 192 WREG32(mmBIF_FB_EN, 0);
196 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
209 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
213 WREG32(mmBIF_FB_EN, tmp);
337 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
338 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
342 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
343 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
347 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
350 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008)
[all...] |
| amdgpu_uvd_v5_0.c | 93 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
264 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
266 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
271 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
272 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
276 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
277 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
282 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
283 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
285 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config)
[all...] |
| amdgpu_vce_v3_0.c | 90 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
92 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
101 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
122 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
124 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
133 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
153 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
155 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
158 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
160 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr))
[all...] |
| amdgpu_gmc_v7_0.c | 104 WREG32(mmBIF_FB_EN, 0);
108 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
121 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
125 WREG32(mmBIF_FB_EN, tmp);
212 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
213 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
217 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
218 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
222 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
225 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008)
[all...] |
| amdgpu_umc_v6_0.c | 37 WREG32((i*0x100000 + 0x5010c + j*0x2000)/4, 0x1002);
|
| amdgpu_amdkfd_gfx_v7.c | 129 WREG32(mmSRBM_GFX_CNTL, value);
136 WREG32(mmSRBM_GFX_CNTL, 0);
166 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
167 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
168 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
169 WREG32(mmSH_MEM_BASES, sh_mem_bases);
188 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
192 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
195 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
211 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
[all...] |
| amdgpu_amdkfd_gfx_v8.c | 86 WREG32(mmSRBM_GFX_CNTL, value);
93 WREG32(mmSRBM_GFX_CNTL, 0);
123 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
124 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
125 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
126 WREG32(mmSH_MEM_BASES, sh_mem_bases);
146 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
150 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
153 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
169 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK
[all...] |
| amdgpu_uvd_v4_2.c | 95 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
273 WREG32(mmUVD_CGC_GATE, 0);
280 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
290 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
291 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
293 WREG32(mmUVD_LMI_CTRL, 0x203108);
296 WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
298 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
299 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
300 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040)
[all...] |
