Searched refs:sc_clk (Results 1 - 25 of 64) sorted by relevance

123

/src/sys/arch/arm/xilinx/
H A Dzynq7000_clkc.c139 struct clk sc_clk[num_clkid]; member in struct:zynq7000_clkc_softc
155 if (strcmp(name, sc->sc_clk[clkid].name) == 0) {
156 return &sc->sc_clk[clkid];
195 &sc->sc_clk[clkid_armpll]);
198 &sc->sc_clk[clkid_ddrpll]);
201 &sc->sc_clk[clkid_iopll]);
214 if (clk == &sc->sc_clk[clkid_armpll]) {
216 } else if (clk == &sc->sc_clk[clkid_iopll]) {
218 } else if (clk == &sc->sc_clk[clkid_cpu_6or4x]) {
220 &sc->sc_clk[clkid_cpu_1
[all...]
/src/sys/dev/fdt/
H A Dfixedfactorclock.c73 struct fixedfactorclock_clk sc_clk; member in struct:fixedfactorclock_softc
106 of_getprop_uint32(phandle, "clock-div", &sc->sc_clk.div);
107 of_getprop_uint32(phandle, "clock-mult", &sc->sc_clk.mult);
109 if (sc->sc_clk.div == 0 || sc->sc_clk.mult == 0) {
118 sc->sc_clk.base.domain = &sc->sc_clkdom;
119 sc->sc_clk.base.name = name;
120 clk_attach(&sc->sc_clk.base);
124 sc->sc_clk.mult, sc->sc_clk
[all...]
H A Dfixedclock.c71 struct fixedclock_clk sc_clk; member in struct:fixedclock_softc
108 &sc->sc_clk.rate) != 0) {
112 sc->sc_clk.base.domain = &sc->sc_clkdom;
113 sc->sc_clk.base.name = kmem_asprintf("%s", clkname);
114 clk_attach(&sc->sc_clk.base);
117 aprint_normal(": %u Hz fixed clock (%s)\n", sc->sc_clk.rate, clkname);
131 return &sc->sc_clk.base;
139 if (strcmp(name, sc->sc_clk.base.name) != 0)
142 return &sc->sc_clk.base;
H A Dusbnopphy.c53 struct clk *sc_clk; member in struct:usbnopphy_softc
87 if (sc->sc_clk != NULL) {
88 error = clk_enable(sc->sc_clk);
102 if (sc->sc_clk != NULL)
103 clk_disable(sc->sc_clk);
133 sc->sc_clk = fdtbus_clock_get(phandle, "main_clk");
H A Dmmc_pwrseq_simple.c51 struct clk *sc_clk; member in struct:mmcpwrseq_simple_softc
64 if (sc->sc_clk) {
65 error = clk_enable(sc->sc_clk);
127 sc->sc_clk = fdtbus_clock_get(phandle, "ext_clock");
128 if (sc->sc_clk == NULL) {
/src/sys/arch/riscv/sifive/
H A Dfu540_prci.c80 struct clk sc_clk[num_clkid]; member in struct:fu540_prci_softc
101 if (strcmp(name, sc->sc_clk[clkid].name) == 0) {
102 return &sc->sc_clk[clkid];
136 if (clk == &sc->sc_clk[clkid_corepll] ||
137 clk == &sc->sc_clk[clkid_tlclk]) {
139 if (clk == &sc->sc_clk[clkid_tlclk]) {
143 } else if (clk == &sc->sc_clk[clkid_ddrpll]) {
145 } else if (clk == &sc->sc_clk[clkid_gemgxlpll]) {
159 if (clk == &sc->sc_clk[clkid_corepll] ||
160 clk == &sc->sc_clk[clkid_tlcl
[all...]
/src/sys/arch/arm/imx/
H A Dimxi2cvar.h39 struct clk *sc_clk; member in struct:imxi2c_softc
H A Dimxpwmvar.h41 struct clk *sc_clk; member in struct:imxpwm_softc
/src/sys/arch/arm/nxp/
H A Dimx_i2c.c67 imxsc->sc_clk = fdtbus_clock_get_index(phandle, 0);
68 if (imxsc->sc_clk == NULL) {
73 error = clk_enable(imxsc->sc_clk);
85 clk_get_rate(imxsc->sc_clk), freq);
H A Dimx6_ocotp.c53 struct clk *sc_clk; member in struct:imxocotp_softc
103 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
104 if (sc->sc_clk == NULL) {
109 error = clk_enable(sc->sc_clk);
H A Dimx6_usbphy.c52 struct clk *sc_clk; member in struct:imx6_usbphy_softc
101 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
102 if (sc->sc_clk == NULL) {
124 error = clk_enable(sc->sc_clk);
H A Dimx6_spi.c48 struct clk *sc_clk; member in struct:imxspi_fdt_softc
123 ifsc->sc_clk = fdtbus_clock_get_index(phandle, 0);
124 if (ifsc->sc_clk == NULL) {
129 error = clk_enable(ifsc->sc_clk);
147 sc->sc_freq = clk_get_rate(ifsc->sc_clk);
/src/sys/arch/arm/broadcom/
H A Dbcm2835_cprman.c73 struct cprman_clk sc_clk[CPRMAN_NCLOCK]; member in struct:cprman_softc
92 clk = &sc->sc_clk[id];
109 for (n = 0; n < __arraycount(sc->sc_clk); n++) {
110 if (sc->sc_clk[n].base.name == NULL)
112 if (strcmp(sc->sc_clk[n].base.name, name) == 0)
113 return &sc->sc_clk[n].base;
153 sc->sc_clk[id].base.domain = &sc->sc_clkdom;
154 sc->sc_clk[id].base.name = name;
155 sc->sc_clk[id].id = id;
H A Dbcm2835_aux.c89 struct bcmaux_clk sc_clk[BCMAUX_NCLOCK]; member in struct:bcmaux_softc
142 sc->sc_clk[BCMAUX_CLOCK_UART].base.domain = &sc->sc_clkdom;
143 sc->sc_clk[BCMAUX_CLOCK_UART].base.name = "aux_uart";
144 sc->sc_clk[BCMAUX_CLOCK_UART].mask = __BIT(0);
146 sc->sc_clk[BCMAUX_CLOCK_SPI1].base.domain = &sc->sc_clkdom;
147 sc->sc_clk[BCMAUX_CLOCK_SPI1].base.name = "aux_spi1";
148 sc->sc_clk[BCMAUX_CLOCK_SPI1].mask = __BIT(1);
150 sc->sc_clk[BCMAUX_CLOCK_SPI2].base.domain = &sc->sc_clkdom;
151 sc->sc_clk[BCMAUX_CLOCK_SPI2].base.name = "aux_spi2";
152 sc->sc_clk[BCMAUX_CLOCK_SPI
[all...]
H A Dbcm2835_bsc_fdt.c88 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
89 if (sc->sc_clk == NULL) {
94 if (clk_enable(sc->sc_clk) != 0) {
99 sc->sc_frequency = clk_get_rate(sc->sc_clk);
/src/sys/arch/arm/fdt/
H A Da9ptmr_fdt.c57 struct clk *sc_clk; member in struct:a9ptmr_fdt_softc
88 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
89 if (sc->sc_clk == NULL) {
93 if (clk_enable(sc->sc_clk) != 0) {
98 uint32_t rate = clk_get_rate(sc->sc_clk);
165 rate = clk_get_rate(sc->sc_clk);
H A Da9tmr_fdt.c57 struct clk *sc_clk; member in struct:a9tmr_fdt_softc
88 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
89 if (sc->sc_clk == NULL) {
93 if (clk_enable(sc->sc_clk) != 0) {
98 uint32_t rate = clk_get_rate(sc->sc_clk);
165 rate = clk_get_rate(sc->sc_clk);
/src/sys/arch/arm/nvidia/
H A Dtegra_fuse.c52 struct clk *sc_clk; member in struct:tegra_fuse_softc
88 sc->sc_clk = fdtbus_clock_get(faa->faa_phandle, "fuse");
89 if (sc->sc_clk == NULL) {
125 clk_enable(fuse_softc->sc_clk);
127 clk_disable(fuse_softc->sc_clk);
H A Dtegra_sdhc.c62 struct clk *sc_clk; member in struct:tegra_sdhc_softc
189 sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0);
190 if (sc->sc_clk == NULL) {
202 error = clk_set_rate(sc->sc_clk, 100000000);
204 error = clk_set_rate(sc->sc_clk, 204000000);
210 error = clk_enable(sc->sc_clk);
217 sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000;
/src/sys/arch/arm/ti/
H A Dti_div_clock.c78 struct clk sc_clk; member in struct:ti_div_clock_softc
124 sc->sc_clk.domain = &sc->sc_clkdom;
125 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
126 clk_attach(&sc->sc_clk);
129 aprint_normal(": TI divider clock (%s)\n", sc->sc_clk.name);
140 return &sc->sc_clk;
148 return &sc->sc_clk;
H A Dti_gate_clock.c73 struct clk sc_clk; member in struct:ti_gate_clock_softc
133 sc->sc_clk.domain = &sc->sc_clkdom;
134 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
135 clk_attach(&sc->sc_clk);
138 aprint_normal(": TI gate clock (%s)\n", sc->sc_clk.name);
149 return &sc->sc_clk;
157 return &sc->sc_clk;
H A Dti_comp_clock.c75 struct clk sc_clk; member in struct:ti_comp_clock_softc
113 sc->sc_clk.domain = &sc->sc_clkdom;
114 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
115 clk_attach(&sc->sc_clk);
118 aprint_normal(": TI composite clock (%s)\n", sc->sc_clk.name);
129 return &sc->sc_clk;
137 return &sc->sc_clk;
H A Dti_mux_clock.c72 struct clk sc_clk; member in struct:ti_mux_clock_softc
140 sc->sc_clk.domain = &sc->sc_clkdom;
141 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
142 clk_attach(&sc->sc_clk);
145 aprint_normal(": TI mux clock (%s)\n", sc->sc_clk.name);
156 return &sc->sc_clk;
164 return &sc->sc_clk;
/src/sys/arch/arm/sunxi/
H A Dsun8i_a23_apbclk.c74 struct clk sc_clk; member in struct:sun8i_a23_apbclk_softc
125 sc->sc_clk.domain = &sc->sc_clkdom;
126 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
143 return &sc->sc_clk;
151 if (strcmp(name, sc->sc_clk.name) != 0)
154 return &sc->sc_clk;
H A Dsun9i_a80_cpusclk.c77 struct clk sc_clk; member in struct:sun9i_a80_cpusclk_softc
126 sc->sc_clk.domain = &sc->sc_clkdom;
127 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
144 return &sc->sc_clk;
152 if (strcmp(name, sc->sc_clk.name) != 0)
155 return &sc->sc_clk;

Completed in 20 milliseconds

123