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    Searched refs:sc_clk (Results 1 - 25 of 62) sorted by relevancy

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  /src/sys/arch/arm/xilinx/
zynq7000_clkc.c 139 struct clk sc_clk[num_clkid]; member in struct:zynq7000_clkc_softc
155 if (strcmp(name, sc->sc_clk[clkid].name) == 0) {
156 return &sc->sc_clk[clkid];
195 &sc->sc_clk[clkid_armpll]);
198 &sc->sc_clk[clkid_ddrpll]);
201 &sc->sc_clk[clkid_iopll]);
214 if (clk == &sc->sc_clk[clkid_armpll]) {
216 } else if (clk == &sc->sc_clk[clkid_iopll]) {
218 } else if (clk == &sc->sc_clk[clkid_cpu_6or4x]) {
220 &sc->sc_clk[clkid_cpu_1x])
    [all...]
  /src/sys/dev/fdt/
fixedfactorclock.c 73 struct fixedfactorclock_clk sc_clk; member in struct:fixedfactorclock_softc
106 of_getprop_uint32(phandle, "clock-div", &sc->sc_clk.div);
107 of_getprop_uint32(phandle, "clock-mult", &sc->sc_clk.mult);
109 if (sc->sc_clk.div == 0 || sc->sc_clk.mult == 0) {
118 sc->sc_clk.base.domain = &sc->sc_clkdom;
119 sc->sc_clk.base.name = name;
120 clk_attach(&sc->sc_clk.base);
124 sc->sc_clk.mult, sc->sc_clk.div)
    [all...]
fixedclock.c 71 struct fixedclock_clk sc_clk; member in struct:fixedclock_softc
108 &sc->sc_clk.rate) != 0) {
112 sc->sc_clk.base.domain = &sc->sc_clkdom;
113 sc->sc_clk.base.name = kmem_asprintf("%s", clkname);
114 clk_attach(&sc->sc_clk.base);
117 aprint_normal(": %u Hz fixed clock (%s)\n", sc->sc_clk.rate, clkname);
131 return &sc->sc_clk.base;
139 if (strcmp(name, sc->sc_clk.base.name) != 0)
142 return &sc->sc_clk.base;
usbnopphy.c 53 struct clk *sc_clk; member in struct:usbnopphy_softc
87 if (sc->sc_clk != NULL) {
88 error = clk_enable(sc->sc_clk);
102 if (sc->sc_clk != NULL)
103 clk_disable(sc->sc_clk);
133 sc->sc_clk = fdtbus_clock_get(phandle, "main_clk");
mmc_pwrseq_simple.c 51 struct clk *sc_clk; member in struct:mmcpwrseq_simple_softc
64 if (sc->sc_clk) {
65 error = clk_enable(sc->sc_clk);
127 sc->sc_clk = fdtbus_clock_get(phandle, "ext_clock");
128 if (sc->sc_clk == NULL) {
  /src/sys/arch/riscv/sifive/
fu540_prci.c 80 struct clk sc_clk[num_clkid]; member in struct:fu540_prci_softc
101 if (strcmp(name, sc->sc_clk[clkid].name) == 0) {
102 return &sc->sc_clk[clkid];
136 if (clk == &sc->sc_clk[clkid_corepll] ||
137 clk == &sc->sc_clk[clkid_tlclk]) {
139 if (clk == &sc->sc_clk[clkid_tlclk]) {
143 } else if (clk == &sc->sc_clk[clkid_ddrpll]) {
145 } else if (clk == &sc->sc_clk[clkid_gemgxlpll]) {
159 if (clk == &sc->sc_clk[clkid_corepll] ||
160 clk == &sc->sc_clk[clkid_tlclk])
    [all...]
  /src/sys/arch/arm/imx/
imxi2cvar.h 39 struct clk *sc_clk; member in struct:imxi2c_softc
imxpwmvar.h 41 struct clk *sc_clk; member in struct:imxpwm_softc
  /src/sys/arch/arm/nxp/
imx_i2c.c 67 imxsc->sc_clk = fdtbus_clock_get_index(phandle, 0);
68 if (imxsc->sc_clk == NULL) {
73 error = clk_enable(imxsc->sc_clk);
85 clk_get_rate(imxsc->sc_clk), freq);
imx6_usbphy.c 52 struct clk *sc_clk; member in struct:imx6_usbphy_softc
101 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
102 if (sc->sc_clk == NULL) {
124 error = clk_enable(sc->sc_clk);
imx6_ocotp.c 53 struct clk *sc_clk; member in struct:imxocotp_softc
103 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
104 if (sc->sc_clk == NULL) {
109 error = clk_enable(sc->sc_clk);
imx6_spi.c 48 struct clk *sc_clk; member in struct:imxspi_fdt_softc
123 ifsc->sc_clk = fdtbus_clock_get_index(phandle, 0);
124 if (ifsc->sc_clk == NULL) {
129 error = clk_enable(ifsc->sc_clk);
147 sc->sc_freq = clk_get_rate(ifsc->sc_clk);
imx6_pwm.c 132 sc->sc_clk = fdtbus_clock_get(phandle, "per");
133 if (sc->sc_clk == NULL) {
137 sc->sc_freq = clk_get_rate(sc->sc_clk);
  /src/sys/arch/arm/broadcom/
bcm2835_cprman.c 73 struct cprman_clk sc_clk[CPRMAN_NCLOCK]; member in struct:cprman_softc
92 clk = &sc->sc_clk[id];
109 for (n = 0; n < __arraycount(sc->sc_clk); n++) {
110 if (sc->sc_clk[n].base.name == NULL)
112 if (strcmp(sc->sc_clk[n].base.name, name) == 0)
113 return &sc->sc_clk[n].base;
153 sc->sc_clk[id].base.domain = &sc->sc_clkdom;
154 sc->sc_clk[id].base.name = name;
155 sc->sc_clk[id].id = id;
bcm2835_aux.c 89 struct bcmaux_clk sc_clk[BCMAUX_NCLOCK]; member in struct:bcmaux_softc
142 sc->sc_clk[BCMAUX_CLOCK_UART].base.domain = &sc->sc_clkdom;
143 sc->sc_clk[BCMAUX_CLOCK_UART].base.name = "aux_uart";
144 sc->sc_clk[BCMAUX_CLOCK_UART].mask = __BIT(0);
146 sc->sc_clk[BCMAUX_CLOCK_SPI1].base.domain = &sc->sc_clkdom;
147 sc->sc_clk[BCMAUX_CLOCK_SPI1].base.name = "aux_spi1";
148 sc->sc_clk[BCMAUX_CLOCK_SPI1].mask = __BIT(1);
150 sc->sc_clk[BCMAUX_CLOCK_SPI2].base.domain = &sc->sc_clkdom;
151 sc->sc_clk[BCMAUX_CLOCK_SPI2].base.name = "aux_spi2";
152 sc->sc_clk[BCMAUX_CLOCK_SPI2].mask = __BIT(2)
    [all...]
bcm2835_bsc_fdt.c 88 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
89 if (sc->sc_clk == NULL) {
94 if (clk_enable(sc->sc_clk) != 0) {
99 sc->sc_frequency = clk_get_rate(sc->sc_clk);
  /src/sys/arch/arm/fdt/
a9ptmr_fdt.c 57 struct clk *sc_clk; member in struct:a9ptmr_fdt_softc
88 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
89 if (sc->sc_clk == NULL) {
93 if (clk_enable(sc->sc_clk) != 0) {
98 uint32_t rate = clk_get_rate(sc->sc_clk);
165 rate = clk_get_rate(sc->sc_clk);
a9tmr_fdt.c 57 struct clk *sc_clk; member in struct:a9tmr_fdt_softc
88 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
89 if (sc->sc_clk == NULL) {
93 if (clk_enable(sc->sc_clk) != 0) {
98 uint32_t rate = clk_get_rate(sc->sc_clk);
165 rate = clk_get_rate(sc->sc_clk);
  /src/sys/arch/arm/nvidia/
tegra_fuse.c 52 struct clk *sc_clk; member in struct:tegra_fuse_softc
88 sc->sc_clk = fdtbus_clock_get(faa->faa_phandle, "fuse");
89 if (sc->sc_clk == NULL) {
125 clk_enable(fuse_softc->sc_clk);
127 clk_disable(fuse_softc->sc_clk);
tegra_sdhc.c 62 struct clk *sc_clk; member in struct:tegra_sdhc_softc
189 sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0);
190 if (sc->sc_clk == NULL) {
202 error = clk_set_rate(sc->sc_clk, 100000000);
204 error = clk_set_rate(sc->sc_clk, 204000000);
210 error = clk_enable(sc->sc_clk);
217 sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000;
  /src/sys/arch/arm/ti/
ti_div_clock.c 75 struct clk sc_clk; member in struct:ti_div_clock_softc
121 sc->sc_clk.domain = &sc->sc_clkdom;
122 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
123 clk_attach(&sc->sc_clk);
126 aprint_normal(": TI divider clock (%s)\n", sc->sc_clk.name);
137 return &sc->sc_clk;
145 return &sc->sc_clk;
ti_mux_clock.c 72 struct clk sc_clk; member in struct:ti_mux_clock_softc
139 sc->sc_clk.domain = &sc->sc_clkdom;
140 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
141 clk_attach(&sc->sc_clk);
144 aprint_normal(": TI mux clock (%s)\n", sc->sc_clk.name);
155 return &sc->sc_clk;
163 return &sc->sc_clk;
  /src/sys/arch/arm/sunxi/
sun8i_a23_apbclk.c 74 struct clk sc_clk; member in struct:sun8i_a23_apbclk_softc
125 sc->sc_clk.domain = &sc->sc_clkdom;
126 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
143 return &sc->sc_clk;
151 if (strcmp(name, sc->sc_clk.name) != 0)
154 return &sc->sc_clk;
sun9i_a80_cpusclk.c 77 struct clk sc_clk; member in struct:sun9i_a80_cpusclk_softc
126 sc->sc_clk.domain = &sc->sc_clkdom;
127 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
144 return &sc->sc_clk;
152 if (strcmp(name, sc->sc_clk.name) != 0)
155 return &sc->sc_clk;
  /src/sys/arch/arm/amlogic/
mesongxl_usb2phy.c 61 struct clk *sc_clk; member in struct:mesongxl_usb2phy_softc
167 sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
168 if (sc->sc_clk == NULL) {
180 if (clk_enable(sc->sc_clk) != 0) {

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