Searched refs:SS3_TCY_ADDR_MODE_SHIFT (Results 1 - 24 of 24) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_video.c168 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
263 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
271 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
279 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
H A Di915_reg.h851 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
H A Di915_render.c306 pI830->samplerstate[unit * 3 + 1] |= wrap_mode << SS3_TCY_ADDR_MODE_SHIFT;
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_video.c193 SS3_TCY_ADDR_MODE_SHIFT) |
291 SS3_TCY_ADDR_MODE_SHIFT) |
301 SS3_TCY_ADDR_MODE_SHIFT) |
311 SS3_TCY_ADDR_MODE_SHIFT) |
H A Di915_reg.h824 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
H A Di915_render.c378 wrap_mode << SS3_TCY_ADDR_MODE_SHIFT;
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_video.c193 SS3_TCY_ADDR_MODE_SHIFT) |
291 SS3_TCY_ADDR_MODE_SHIFT) |
301 SS3_TCY_ADDR_MODE_SHIFT) |
311 SS3_TCY_ADDR_MODE_SHIFT) |
H A Di915_reg.h824 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
H A Di915_render.c378 wrap_mode << SS3_TCY_ADDR_MODE_SHIFT;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_state_sampler.c119 state[1] |= (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT);
H A Di915_reg.h814 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
H A Di915_state.c318 (translate_wrap_mode(wt) << SS3_TCY_ADDR_MODE_SHIFT) |
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di915_texstate.c352 (translate_wrap_mode(wt) << SS3_TCY_ADDR_MODE_SHIFT) |
H A Di915_reg.h709 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di915_texstate.c352 (translate_wrap_mode(wt) << SS3_TCY_ADDR_MODE_SHIFT) |
H A Di915_reg.h709 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_reg.h824 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_reg.h824 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_reg.h839 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
H A Di915_state.c266 (translate_wrap_mode(wt) << SS3_TCY_ADDR_MODE_SHIFT) |
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h827 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
H A Dgen3_render.c347 TEXCOORDMODE_##x << SS3_TCY_ADDR_MODE_SHIFT)
367 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT)
5175 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5290 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5298 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5306 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h827 #define SS3_TCY_ADDR_MODE_SHIFT 9 macro
H A Dgen3_render.c347 TEXCOORDMODE_##x << SS3_TCY_ADDR_MODE_SHIFT)
367 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT)
5105 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5220 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5228 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5236 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |

Completed in 53 milliseconds