Searched refs:TEXCOORDMODE_CLAMP_EDGE (Results 1 - 24 of 24) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_video.c167 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
168 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
262 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
263 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
270 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
271 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
278 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
279 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
H A Di915_reg.h847 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
H A Di915_render.c271 wrap_mode = TEXCOORDMODE_CLAMP_EDGE;
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_video.c190 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
192 (TEXCOORDMODE_CLAMP_EDGE <<
288 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
290 (TEXCOORDMODE_CLAMP_EDGE <<
298 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
300 (TEXCOORDMODE_CLAMP_EDGE <<
308 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
310 (TEXCOORDMODE_CLAMP_EDGE <<
H A Di915_reg.h820 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
H A Di915_render.c330 wrap_mode = TEXCOORDMODE_CLAMP_EDGE;
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_video.c190 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
192 (TEXCOORDMODE_CLAMP_EDGE <<
288 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
290 (TEXCOORDMODE_CLAMP_EDGE <<
298 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
300 (TEXCOORDMODE_CLAMP_EDGE <<
308 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
310 (TEXCOORDMODE_CLAMP_EDGE <<
H A Di915_reg.h820 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
H A Di915_render.c330 wrap_mode = TEXCOORDMODE_CLAMP_EDGE;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_state_sampler.c118 state[1] |= (TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT);
119 state[1] |= (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT);
120 state[1] |= (TEXCOORDMODE_CLAMP_EDGE << SS3_TCZ_ADDR_MODE_SHIFT);
H A Di915_state.c60 return TEXCOORDMODE_CLAMP_EDGE; /* not quite correct */
62 return TEXCOORDMODE_CLAMP_EDGE;
H A Di915_reg.h810 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di915_texstate.c121 return TEXCOORDMODE_CLAMP_EDGE; /* not quite correct */
123 return TEXCOORDMODE_CLAMP_EDGE;
318 /* Only support TEXCOORDMODE_CLAMP_EDGE and TEXCOORDMODE_CUBE (not
H A Di915_reg.h705 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di915_texstate.c121 return TEXCOORDMODE_CLAMP_EDGE; /* not quite correct */
123 return TEXCOORDMODE_CLAMP_EDGE;
318 /* Only support TEXCOORDMODE_CLAMP_EDGE and TEXCOORDMODE_CUBE (not
H A Di915_reg.h705 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_state.c58 return TEXCOORDMODE_CLAMP_EDGE; /* not quite correct */
60 return TEXCOORDMODE_CLAMP_EDGE;
H A Di915_reg.h835 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_reg.h820 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_reg.h820 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h823 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
H A Dgen3_render.c5174 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
5175 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5289 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
5290 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5297 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
5298 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5305 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
5306 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h823 #define TEXCOORDMODE_CLAMP_EDGE 2 macro
H A Dgen3_render.c5104 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
5105 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5219 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
5220 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5227 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
5228 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |
5235 OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
5236 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT) |

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