Searched refs:interleaved (Results 1 - 22 of 22) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_draw_upload.c468 GLuint interleaved = 0; local in function:brw_prepare_vertices
589 * when we've decided if we're doing interleaved or not.
592 interleaved = glbinding->Stride;
595 else if (interleaved != glbinding->Stride ||
599 glattrib->Format._ElementSize > interleaved)
604 * interleaved upload optimization. The second case can most
616 interleaved = 0;
653 if (interleaved) {
655 /* All uploads are interleaved, so upload the arrays together as
656 * interleaved
[all...]
/xsrc/external/mit/MesaLib/dist/docs/isl/
H A Dtiling.rst112 width, as the stencil buffer is stored with two rows interleaved.
115 mean that "the stencil buffer is stored with two rows interleaved"? The
119 x 32rows) but every pair of rows in the stencil buffer is interleaved into
240 width, as the stencil buffer is stored with two rows interleaved.
243 interleaved". More accurately, a W-tiled buffer can be viewed as a Y-tiled
244 buffer with each set of 4 W-tiled lines interleaved to form 2 Y-tiled lines. In
H A Dunits.rst62 which allows us to express both the array and interleaved cases. Most of the
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D18.1.4.rst99 - i965: Fix output register sizes when variable ranges are interleaved
H A D9.1.5.rst88 - i965: Be more careful with the interleaved user array upload
H A D17.1.4.rst123 - i965: Disable the interleaved vertex optimization when instancing
124 - i965: Set step_rate = 0 for interleaved vertex buffers
H A D7.10.3.rst294 - i965: Align interleaved URB write length to 2
H A D20.2.0.rst3288 - gallium/u_vbuf: add a faster path for uploading non-interleaved attribs
H A D20.3.0.rst3738 - zink: use u_transfer_helper to split/merge interleaved depth/stencil formats
/xsrc/external/mit/mesa-demos/dist/src/trivial/
H A DMakefile.am123 tri-array-interleaved \
H A DMakefile.in174 @HAVE_GLUT_TRUE@ tri-array-interleaved$(EXEEXT) \
513 tri_array_interleaved_SOURCES = tri-array-interleaved.c
514 tri_array_interleaved_OBJECTS = tri-array-interleaved.$(OBJEXT)
836 tri-array-interleaved.c tri-blend.c tri-blend-color.c \
887 tri-array-interleaved.c tri-blend.c tri-blend-color.c \
1544 tri-array-interleaved$(EXEEXT): $(tri_array_interleaved_OBJECTS) $(tri_array_interleaved_DEPENDENCIES) $(EXTRA_tri_array_interleaved_DEPENDENCIES)
1545 @rm -f tri-array-interleaved$(EXEEXT)
1986 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tri-array-interleaved.Po@am__quote@
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_vec4_gs_visitor.cpp57 attribute_to_hw_reg(int attr, brw_reg_type type, bool interleaved) argument
62 if (interleaved) {
76 * If interleaved is true, then each attribute takes up half a register, with
79 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
130 * to be interleaved, so one register contains two attribute slots.
925 * do interleaved outputs, but currently, the vec4 visitor and generator
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_vec4_gs_visitor.cpp58 attribute_to_hw_reg(int attr, brw_reg_type type, bool interleaved) argument
63 if (interleaved) {
77 * If interleaved is true, then each attribute takes up half a register, with
80 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
131 * to be interleaved, so one register contains two attribute slots.
906 * do interleaved outputs, but currently, the vec4 visitor and generator
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/modes/
H A Dxf86Cursors.c143 const Bool interleaved = local in function:cursor_bitpos
151 const int stride = interleaved ? width / 4 : width / 8;
/xsrc/external/mit/xorg-server/dist/hw/xfree86/modes/
H A Dxf86Cursors.c145 const Bool interleaved = local in function:cursor_bitpos
153 const int stride = interleaved ? width / 4 : width / 8;
/xsrc/external/mit/MesaLib/dist/docs/gallium/
H A Dbuffermapping.rst54 incrementing ``glBufferSubData()`` offsets interleaved with draws from that data
384 interleaved with drawing.
H A Dscreen.rst399 * ``PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS``: Whether interleaved stream
/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/inc/
H A Daddrinterface.h505 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding member in struct:_ADDR_SURFACE_FLAGS::__anona73c1f960508
908 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
909 /// Compute engine clear can't be used if htile is interleaved
2356 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding member in struct:_ADDR2_SURFACE_FLAGS::__anona73c1f961708
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/inc/
H A Daddrinterface.h508 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding member in struct:_ADDR_SURFACE_FLAGS::__anond65a1f890508
915 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
916 /// Compute engine clear can't be used if htile is interleaved
2404 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding member in struct:_ADDR2_SURFACE_FLAGS::__anond65a1f891708
/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/r800/
H A Dsiaddrlib.cpp1658 if (flags.interleaved)
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/r800/
H A Dsiaddrlib.cpp1658 if (flags.interleaved)
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/
H A Dscreen.rst374 * ``PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS``: Whether interleaved stream

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