Searched refs:pm4 (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_cp_reg_shadowing.c30 static void si_build_load_reg(struct si_screen *sscreen, struct si_pm4_state *pm4, argument
59 si_pm4_cmd_add(pm4, PKT3(packet, 1 + num_ranges * 2, 0));
60 si_pm4_cmd_add(pm4, gpu_address);
61 si_pm4_cmd_add(pm4, gpu_address >> 32);
63 si_pm4_cmd_add(pm4, (ranges[i].offset - offset) / 4);
64 si_pm4_cmd_add(pm4, ranges[i].size / 4);
71 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); local in function:si_create_shadowing_ib_preamble
74 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0));
75 si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
79 si_pm4_cmd_add(pm4, PKT
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H A Dsi_pm4.h54 uint32_t pm4[SI_PM4_MAX_DW]; member in struct:si_pm4_state
H A Dsi_pm4.c40 state->pm4[state->ndw++] = dw;
48 state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate);
84 state->pm4[state->ndw++] = reg;
88 state->pm4[state->ndw++] = val;
126 radeon_emit_array(state->pm4, state->ndw);
H A Dsi_state.c438 struct si_pm4_state *pm4 = &blend->pm4; local in function:si_create_blend_state_mode
470 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
476 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
512 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
522 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
588 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
624 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]);
631 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTRO
915 struct si_pm4_state *pm4 = &rs->pm4; local in function:si_create_rs_state
1054 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i]; local in function:si_create_rs_state
1260 struct si_pm4_state *pm4 = &dsa->pm4; local in function:si_create_dsa_state
5283 si_set_grbm_gfx_index(struct si_context * sctx,struct si_pm4_state * pm4,unsigned value) argument
5289 si_set_grbm_gfx_index_se(struct si_context * sctx,struct si_pm4_state * pm4,unsigned se) argument
5298 si_write_harvested_raster_configs(struct si_context * sctx,struct si_pm4_state * pm4,unsigned raster_config,unsigned raster_config_1) argument
5318 si_set_raster_config(struct si_context * sctx,struct si_pm4_state * pm4) argument
5343 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); local in function:si_init_cs_preamble_state
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H A Dsi_state_shaders.c473 si_pm4_clear_state(&shader->pm4);
474 shader->pm4.is_shader = true;
475 return &shader->pm4;
530 struct si_pm4_state *pm4; local in function:si_shader_ls
535 pm4 = si_get_shader_pm4_state(shader);
536 if (!pm4)
540 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
553 struct si_pm4_state *pm4; local in function:si_shader_hs
556 pm4 = si_get_shader_pm4_state(shader);
557 if (!pm4)
628 struct si_pm4_state *pm4; local in function:si_shader_es
843 struct si_pm4_state *pm4; local in function:si_shader_gs
1160 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader); local in function:gfx10_shader_ngg
1415 struct si_pm4_state *pm4; local in function:si_shader_vs
1614 struct si_pm4_state *pm4; local in function:si_shader_ps
3571 struct si_pm4_state *pm4; local in function:si_update_gs_ring_buffers
3960 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); local in function:si_init_tess_factor_ring
3991 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); local in function:si_build_vgt_shader_config
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H A Dsi_state.h54 struct si_pm4_state pm4; member in struct:si_state_blend
72 struct si_pm4_state pm4; member in struct:si_state_rasterizer
125 struct si_pm4_state pm4; member in struct:si_state_dsa
H A Dsi_shader.h766 struct si_pm4_state pm4; /* base class */ member in struct:si_shader
H A Dsi_state_draw.cpp239 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index]; local in function:si_update_shaders
240 if (unlikely(!*pm4))
241 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
242 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
H A Dsi_debug.c417 ac_parse_ib(f, ctx->cs_preamble_state->pm4, ctx->cs_preamble_state->ndw, NULL, 0,
421 ac_parse_ib(f, ctx->cs_preamble_gs_rings->pm4, ctx->cs_preamble_gs_rings->ndw, NULL, 0,
/xsrc/external/mit/libdrm/dist/tests/amdgpu/
H A Dbasic_tests.c1052 uint32_t *pm4; local in function:amdgpu_bo_eviction_test
1062 pm4 = calloc(pm4_dw, sizeof(*pm4));
1063 CU_ASSERT_NOT_EQUAL(pm4, NULL);
1138 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0,
1140 pm4[i++] = 0xffffffff & bo2_mc;
1141 pm4[i++] = 0xffffffff & bo1_mc;
1142 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
1143 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
1145 pm4[
1572 uint32_t *pm4; local in function:amdgpu_command_submission_write_linear_helper_with_secure
1781 uint32_t *pm4; local in function:amdgpu_command_submission_const_fill_helper
1914 uint32_t *pm4; local in function:amdgpu_command_submission_copy_linear_helper
2182 uint32_t *pm4 = NULL; local in function:amdgpu_userptr_test
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H A Damdgpu_stress.c145 uint32_t *pm4; variable in typeref:typename:uint32_t *
202 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0,
204 pm4[i++] = 0xffffffff & dst;
205 pm4[i++] = 0xffffffff & src;
206 pm4[i++] = (0xffffffff00000000 & dst) >> 32;
207 pm4[i++] = (0xffffffff00000000 & src) >> 32;
209 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY,
213 pm4[i++] = bytes - 1;
215 pm4[i++] = bytes;
216 pm4[
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_shaders.c341 struct si_pm4_state *pm4)
399 assert(pm4->shader);
400 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
423 struct si_pm4_state *pm4)
443 assert(pm4->shader);
444 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
450 if (shader->pm4)
451 si_pm4_clear_state(shader->pm4);
453 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
455 if (shader->pm4) {
339 si_set_tesseval_regs(struct si_screen * sscreen,const struct si_shader_selector * tes,struct si_pm4_state * pm4) argument
420 polaris_set_vgt_vertex_reuse(struct si_screen * sscreen,struct si_shader_selector * sel,struct si_shader * shader,struct si_pm4_state * pm4) argument
472 struct si_pm4_state *pm4; local in function:si_shader_ls
505 struct si_pm4_state *pm4; local in function:si_shader_hs
584 struct si_pm4_state *pm4; local in function:si_shader_es
836 struct si_pm4_state *pm4; local in function:si_shader_gs
1019 struct si_pm4_state *pm4; local in function:si_shader_vs
1203 struct si_pm4_state *pm4; local in function:si_shader_ps
2911 struct si_pm4_state *pm4; local in function:si_update_gs_ring_buffers
3302 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index]; local in function:si_update_vgt_shader_config
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H A Dsi_pm4.c37 state->pm4[state->ndw++] = dw;
44 state->pm4[state->last_pm4] =
134 radeon_emit_array(cs, state->pm4, state->ndw);
183 state->pm4[i] = 0x80000000; /* type2 nop packet */
186 state->pm4[i] = 0xffff1000; /* type3 nop packet */
190 0, aligned_ndw *4, state->pm4);
H A Dsi_state.c457 struct si_pm4_state *pm4 = &blend->pm4; local in function:si_create_blend_state_mode
475 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
524 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
534 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
598 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
631 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
640 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
852 struct si_pm4_state *pm4 local in function:si_create_rs_state
952 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i]; local in function:si_create_rs_state
1167 struct si_pm4_state *pm4 = &dsa->pm4; local in function:si_create_dsa_state
4856 si_set_grbm_gfx_index(struct si_context * sctx,struct si_pm4_state * pm4,unsigned value) argument
4864 si_set_grbm_gfx_index_se(struct si_context * sctx,struct si_pm4_state * pm4,unsigned se) argument
4876 si_write_harvested_raster_configs(struct si_context * sctx,struct si_pm4_state * pm4,unsigned raster_config,unsigned raster_config_1) argument
4901 si_set_raster_config(struct si_context * sctx,struct si_pm4_state * pm4) argument
4928 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); local in function:si_init_config
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H A Dsi_pm4.h55 uint32_t pm4[SI_PM4_MAX_DW]; member in struct:si_pm4_state
H A Dsi_state.h49 struct si_pm4_state pm4; member in struct:si_state_blend
65 struct si_pm4_state pm4; member in struct:si_state_rasterizer
113 struct si_pm4_state pm4; member in struct:si_state_dsa
H A Dsi_shader.h602 struct si_pm4_state *pm4; member in struct:si_shader
H A Dsi_debug.c412 ac_parse_ib(f, ctx->init_config->pm4, ctx->init_config->ndw,
417 ac_parse_ib(f, ctx->init_config_gs_rings->pm4,
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dmsm_kgsl.h373 unsigned int pm4; member in struct:kgsl_ucode_version
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.3.0.rst2613 - radeonsi: correctly use cs instead of gfx_cs in build pm4 helpers
2675 - radeonsi: unset SI_PREFETCH_* only when we unbind pm4 shader states
H A D20.2.0.rst3447 - freedreno: android: add adreno-pm4-pack.xml.h generation to android build
H A D21.2.0.rst4559 - freedreno/tu+drm: Extract out pm4 pkt header helpers
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json17608 "description": "radeonsi: decrease the size of si_pm4_state::pm4 except for cs_preamble_state",
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