Searched refs:vec4_instruction (Results 1 - 25 of 58) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_vec4.h157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
163 bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
173 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
178 vec4_instruction *emi
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H A Dbrw_vec4_visitor.cpp31 vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst, function in class:brw::vec4_instruction
65 vec4_instruction *
66 vec4_visitor::emit(vec4_instruction *inst)
76 vec4_instruction *
77 vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst,
78 vec4_instruction *new_inst)
88 vec4_instruction *
92 return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1, src2));
96 vec4_instruction *
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H A Dbrw_vec4_tes.h57 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
H A Dbrw_vec4_vs.h48 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
H A Dtest_vec4_dead_code_eliminate.cpp80 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */)
138 vec4_instruction *test_cmp =
144 vec4_instruction *test_mov =
150 vec4_instruction *test_sel =
H A Dbrw_ir_vec4.h269 class vec4_instruction : public backend_instruction { class in namespace:brw
271 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
273 vec4_instruction(enum opcode opcode,
369 inline vec4_instruction *
371 vec4_instruction *inst)
381 inline vec4_instruction *
382 set_predicate(enum brw_predicate pred, vec4_instruction *inst)
391 inline vec4_instruction *
392 set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst)
402 inline vec4_instruction *
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H A Dbrw_vec4_cse.cpp41 vec4_instruction *generator;
49 is_expression(const vec4_instruction *const inst)
98 operands_match(const vec4_instruction *a, const vec4_instruction *b)
143 instructions_match(vec4_instruction *a, vec4_instruction *b)
174 foreach_inst_in_block (vec4_instruction, inst, block) {
218 vec4_instruction *copy =
239 vec4_instruction *copy =
253 vec4_instruction *pre
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H A Dbrw_vec4_vs_visitor.cpp46 vec4_instruction *
55 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
78 vec4_instruction *inst = emit_generic_urb_slot(reg, varying, 0);
H A Dbrw_vec4_gs_visitor.h59 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
H A Dbrw_vec4_tcs.h75 virtual vec4_instruction *emit_urb_write_opcode(bool complete) { return NULL; }
H A Dtest_vec4_register_coalesce.cpp85 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */)
137 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
161 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
184 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
202 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
228 vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2));
H A Dbrw_vec4.cpp151 vec4_instruction::is_send_from_grf()
189 vec4_instruction::has_source_and_destination_hazard() const
208 vec4_instruction::size_read(unsigned arg) const
240 vec4_instruction::can_do_source_mods(const struct gen_device_info *devinfo)
255 vec4_instruction::can_do_cmod()
275 vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
312 vec4_instruction::can_change_types() const
331 vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
411 vec4_instruction *imm_inst[4];
415 foreach_inst_in_block_safe(vec4_instruction, ins
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H A Dbrw_vec4_reg_allocate.cpp55 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
75 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
227 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
269 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
303 can_use_scratch_for_source(const vec4_instruction *inst, unsigned i,
316 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev;
318 prev_inst = (vec4_instruction *) prev_inst->prev) {
399 foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
513 foreach_block_and_inst(block, vec4_instruction, ins
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/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_vec4.h157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
163 bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
173 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
178 vec4_instruction *emi
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H A Dbrw_vec4_vs_visitor.cpp46 vec4_instruction *
55 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
78 vec4_instruction *inst = emit_generic_urb_slot(reg, varying, 0);
H A Dbrw_vec4_visitor.cpp31 vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst, function in class:brw::vec4_instruction
65 vec4_instruction *
66 vec4_visitor::emit(vec4_instruction *inst)
76 vec4_instruction *
77 vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst,
78 vec4_instruction *new_inst)
88 vec4_instruction *
92 return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1, src2));
96 vec4_instruction *
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H A Dbrw_vec4_tes.h58 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
H A Dbrw_vec4_vs.h49 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
H A Dtest_vec4_dead_code_eliminate.cpp82 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */)
150 vec4_instruction *test_cmp =
156 vec4_instruction *test_mov =
162 vec4_instruction *test_sel =
H A Dbrw_ir_vec4.h269 class vec4_instruction : public backend_instruction { class in namespace:brw
271 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
273 vec4_instruction(enum opcode opcode,
371 inline vec4_instruction *
373 vec4_instruction *inst)
383 inline vec4_instruction *
384 set_predicate(enum brw_predicate pred, vec4_instruction *inst)
393 inline vec4_instruction *
394 set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst)
404 inline vec4_instruction *
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H A Dbrw_vec4_cse.cpp41 vec4_instruction *generator;
49 is_expression(const vec4_instruction *const inst)
98 operands_match(const vec4_instruction *a, const vec4_instruction *b)
143 instructions_match(vec4_instruction *a, vec4_instruction *b)
174 foreach_inst_in_block (vec4_instruction, inst, block) {
218 vec4_instruction *copy =
239 vec4_instruction *copy =
253 vec4_instruction *pre
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H A Dbrw_vec4_gs_visitor.h60 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
H A Dbrw_vec4_tcs.h75 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) { return NULL; }
H A Dtest_vec4_register_coalesce.cpp85 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */)
148 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
172 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
195 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
213 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
239 vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2));
H A Dbrw_vec4.cpp150 vec4_instruction::is_send_from_grf() const
188 vec4_instruction::has_source_and_destination_hazard() const
207 vec4_instruction::size_read(unsigned arg) const
239 vec4_instruction::can_do_source_mods(const struct intel_device_info *devinfo)
254 vec4_instruction::can_do_cmod()
274 vec4_instruction::can_do_writemask(const struct intel_device_info *devinfo)
310 vec4_instruction::can_change_types() const
329 vec4_instruction::implied_mrf_writes() const
409 vec4_instruction *imm_inst[4];
413 foreach_inst_in_block_safe(vec4_instruction, ins
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