/src/sys/arch/sandpoint/stand/altboot/ |
skg.c | 50 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 229 CSR_WRITE_4(l, SK_RAMCTL, 2); /* enable RAM interface */ 252 CSR_WRITE_4(l, SK_RXMF1_CTRL_TEST, RFCTL_OPERATION_ON); 254 CSR_WRITE_4(l, SK_TXMF1_CTRL_TEST, TFCTL_OPERATION_ON); 274 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_UNRESET); 275 CSR_WRITE_4(l, SK_RXRB1_START, 0); 276 CSR_WRITE_4(l, SK_RXRB1_WR_PTR, 0); 277 CSR_WRITE_4(l, SK_RXRB1_RD_PTR, 0); 278 CSR_WRITE_4(l, SK_RXRB1_END, 0xfff); 279 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_ON) [all...] |
kse.c | 48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 177 CSR_WRITE_4(l, TDLB, VTOPHYS(txd)); 178 CSR_WRITE_4(l, RDLB, VTOPHYS(rxd)); 179 CSR_WRITE_4(l, MDTXC, 07); /* stretch short, add CRC, Tx enable */ 180 CSR_WRITE_4(l, MDRXC, 01); /* Rx enable */ 181 CSR_WRITE_4(l, MDRSC, 01); /* start receiving */ 199 CSR_WRITE_4(l, MDTSC, 01); /* start transmission */ 241 CSR_WRITE_4(l, MDRSC, 01); /* restart receiving */ 254 CSR_WRITE_4(l, MDRSC, 01); /* necessary? */
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rge.c | 51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 173 CSR_WRITE_4(l, RGE_IDR0, reg); 175 CSR_WRITE_4(l, RGE_IDR4, reg); 221 CSR_WRITE_4(l, RGE_TCR, l->tcr); 222 CSR_WRITE_4(l, RGE_RCR, l->rcr); 223 CSR_WRITE_4(l, RGE_TNPDS, VTOPHYS(txd)); 224 CSR_WRITE_4(l, RGE_RDSAR, VTOPHYS(rxd)); 225 CSR_WRITE_4(l, RGE_TNPDS + 4, 0); 226 CSR_WRITE_4(l, RGE_RDSAR + 4, 0); 319 CSR_WRITE_4(l, RGE_PHYAR, v) [all...] |
fxp.c | 93 #define CSR_WRITE_4(l, r, v) out32rb((l)->iobase+(r), (v)) 202 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 220 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 276 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(cbp)); 299 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(cb_ias)); 320 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(rfa)); 351 CSR_WRITE_4(l, FXP_CSR_SCB_GENERAL, VTOPHYS(txd)); 517 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
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pcn.c | 48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 160 CSR_WRITE_4(l, PCN_RDP, 0); 313 CSR_WRITE_4(l, PCN_RAP, r); 320 CSR_WRITE_4(l, PCN_RAP, r); 321 CSR_WRITE_4(l, PCN_RDP, v); 327 CSR_WRITE_4(l, PCN_RAP, r); 334 CSR_WRITE_4(l, PCN_RAP, r); 335 CSR_WRITE_4(l, PCN_BDP, v);
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stg.c | 45 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 234 CSR_WRITE_4(l, STGE_TFDListPtrHi, 0); 235 CSR_WRITE_4(l, STGE_TFDListPtrLo, VTOPHYS(txd)); 236 CSR_WRITE_4(l, STGE_RFDListPtrHi, 0); 237 CSR_WRITE_4(l, STGE_RFDListPtrLo, VTOPHYS(rxd)); 239 CSR_WRITE_4(l, STGE_MACCtrl, 0); /* do IFSSelect(0) first */ 272 CSR_WRITE_4(l, STGE_MACCtrl, macctl); 302 CSR_WRITE_4(l, STGE_DMACtrl, DMAC_TxDMAPollNow); 364 CSR_WRITE_4(l, STGE_AsicCtrl, reg | AC_GlobalReset | AC_RxReset |
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siisata.c | 42 #define CSR_WRITE_4(r,v) out32rb(r,v) 180 CSR_WRITE_4(sc, val | 01); /* perform init */ 182 CSR_WRITE_4(sc, val);
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/src/sys/arch/arm/xscale/ |
ixp425_pci_space.c | 53 #define CSR_WRITE_4(x, v) *(volatile uint32_t *) \ 270 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 271 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); 274 CSR_WRITE_4(PCI_ISR, ISR_PFE); 290 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 291 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); 294 CSR_WRITE_4(PCI_ISR, ISR_PFE); 307 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); 308 CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ); 311 CSR_WRITE_4(PCI_ISR, ISR_PFE) [all...] |
pxa2x0_mci.c | 151 #define CSR_WRITE_4(sc, reg, val) \ 154 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val)) 156 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val)) 173 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 184 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 358 CSR_WRITE_4(sc, MMC_SPI, 0); 359 CSR_WRITE_4(sc, MMC_RESTO, 0x7f); 360 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); 511 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); 512 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START) [all...] |
pxa2x0_i2c.c | 408 #define CSR_WRITE_4(sc,r,v) bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v) 420 CSR_WRITE_4(sc, I2C_ICR, ICR_UR); 421 CSR_WRITE_4(sc, I2C_ISAR, 0); 422 CSR_WRITE_4(sc, I2C_ISR, ISR_ALL); 425 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr); 449 CSR_WRITE_4(sc, I2C_ISR, isr); 458 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_START); 467 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_STOP); 483 CSR_WRITE_4(sc, I2C_IDBR, (addr << 1) | rd_req); 484 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_START | ICR_TB) [all...] |
/src/sys/dev/pci/ |
if_et.c | 243 CSR_WRITE_4(sc, ET_PM, pmcfg); 368 CSR_WRITE_4(sc, ET_MII_CMD, 0); 372 CSR_WRITE_4(sc, ET_MII_ADDR, data); 375 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 400 CSR_WRITE_4(sc, ET_MII_CMD, 0); 414 CSR_WRITE_4(sc, ET_MII_CMD, 0); 418 CSR_WRITE_4(sc, ET_MII_ADDR, data); 421 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val, ET_MII_CTRL_VALUE)); 441 CSR_WRITE_4(sc, ET_MII_CMD, 0); 515 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl) [all...] |
if_alc.c | 218 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 250 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 289 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 318 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 373 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 415 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 421 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 446 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 452 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 632 CSR_WRITE_4(sc, ALC_OPT_CFG, opt) [all...] |
if_bge.c | 607 CSR_WRITE_4(sc, off, val); 616 CSR_WRITE_4(sc, off, val); 953 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 964 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 966 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 967 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 987 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1041 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1247 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1248 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode) [all...] |
if_ti.c | 363 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 413 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 432 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 452 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 454 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 470 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 477 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 532 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 1042 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0) [all...] |
if_ipwreg.h | 328 #define CSR_WRITE_4(sc, reg, val) \ 339 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 344 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 349 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 350 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 354 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
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if_age.c | 358 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 390 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 446 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 449 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 505 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 514 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 571 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 580 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 615 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 617 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR) [all...] |
if_ale.c | 151 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 191 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 248 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 299 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 308 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 1079 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1155 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1295 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1323 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1580 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000) [all...] |
if_iwireg.h | 552 #define CSR_WRITE_4(sc, reg, val) \ 563 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 568 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 573 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 574 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 578 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
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if_ipw.c | 138 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 145 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 209 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1174 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1260 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1297 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1301 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1340 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1504 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1593 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base) [all...] |
if_iwi.c | 153 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); 160 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); 251 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0); 1200 CSR_WRITE_4(sc, IWI_CSR_RX_BASE + i * 4, data->map->dm_segs[0].ds_addr); 1381 CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, 1429 CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, hw); 1485 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0); 1502 CSR_WRITE_4(sc, IWI_CSR_INTR, r); 1550 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, IWI_INTR_MASK); 1577 CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.cur) [all...] |
if_bgevar.h | 100 #define CSR_WRITE_4(sc, reg, val) \ 108 CSR_WRITE_4(sc, reg, val); \ 113 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 120 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
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if_stge.c | 223 #define CSR_WRITE_4(_sc, reg, val) \ 984 CSR_WRITE_4(sc, STGE_DMACtrl, 1474 CSR_WRITE_4(sc, STGE_AsicCtrl, 1563 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 1564 CSR_WRITE_4(sc, STGE_StatisticsMask, 1576 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 1578 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 1581 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 1583 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 1617 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl [all...] |
if_kse.c | 67 #define CSR_WRITE_4(sc, off, val) \ 764 CSR_WRITE_4(sc, TDLB, KSE_CDTXADDR(sc, 0)); 765 CSR_WRITE_4(sc, RDLB, KSE_CDRXADDR(sc, 0)); 813 CSR_WRITE_4(sc, MDTXC, sc->sc_txc); 814 CSR_WRITE_4(sc, MDRXC, sc->sc_rxc); 815 CSR_WRITE_4(sc, MDRSC, 1); 821 CSR_WRITE_4(sc, INTST, ~0); 822 CSR_WRITE_4(sc, INTEN, sc->sc_inten); 854 CSR_WRITE_4(sc, MDTXC, sc->sc_txc); 855 CSR_WRITE_4(sc, MDRXC, sc->sc_rxc) [all...] |
/src/sys/dev/ic/ |
rtl81x9.c | 540 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 541 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 542 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 547 CSR_WRITE_4(sc, RTK_MAR0, 0); 548 CSR_WRITE_4(sc, RTK_MAR4, 0); 578 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 587 CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1])); 588 CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0])); 590 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 591 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]) [all...] |
rtl8169.c | 247 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 273 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 1495 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1841 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1921 CSR_WRITE_4(sc, RTK_IDR0, reg); 1923 CSR_WRITE_4(sc, RTK_IDR4, reg); 1936 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1938 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1941 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1943 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO [all...] |