| /src/sys/arch/arm/imx/ |
| imx23_emireg.h | 52 #define HW_EMI_CTRL_AXI_DEPTH __BITS(27, 26)
55 #define HW_EMI_CTRL_ARB_MODE __BITS(23, 22)
57 #define HW_EMI_CTRL_PORT_PRIORITY_ORDER __BITS(20, 16)
59 #define HW_EMI_CTRL_PRIORITY_WRITE_ITER __BITS(14, 12)
61 #define HW_EMI_CTRL_HIGH_PRIORITY_WRITE __BITS(10, 8)
66 #define HW_EMI_CTRL_RSVD0 __BITS(3, 0)
73 #define HW_EMI_VERSION_MAJOR __BITS(31, 24)
74 #define HW_EMI_VERSION_MINOR __BITS(23, 16)
75 #define HW_EMI_VERSION_STEP __BITS(15, 0)
82 #define HW_DRAM_CTL00_RSVD4 __BITS(31, 25
[all...] |
| imx23_apbxdmareg.h | 45 #define HW_APBX_CH0_CURCMDAR_CMD_ADDR __BITS(31, 0)
52 #define HW_APBX_CH0_NXTCMDAR_CMD_ADDR __BITS(31, 0)
59 #define HW_APBX_CH0_SEMA_RSVD2 __BITS(31, 24)
60 #define HW_APBX_CH0_SEMA_PHORE __BITS(23, 16)
61 #define HW_APBX_CH0_SEMA_RSVD1 __BITS(15, 8)
62 #define HW_APBX_CH0_SEMA_INCREMENT_SEMA __BITS(7, 0)
|
| imx23_apbdma.h | 61 #define NEXTCMDADDR __BITS(31, 0)
66 #define XFER_COUNT __BITS(31, 16)
67 #define CMDPIOWORDS __BITS(15, 12)
68 #define CMDWORD1_RSVD0 __BITS(11, 8)
75 #define COMMAND __BITS(1, 0)
80 #define BUF_ADDR __BITS(31, 0)
85 #define PIOWORD __BITS(31, 0)
|
| imx23_digctlreg.h | 51 #define HW_DIGCTL_CTRL_RSVD2 __BITS(28, 27)
64 #define HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL __BITS(14, 13)
91 #define HW_DIGCTL_STATUS_RSVD2 __BITS(27, 11)
99 #define HW_DIGCTL_STATUS_PACKAGE_TYPE __BITS(3, 1)
110 #define HW_DIGCTL_HCLKCOUNT_COUNT __BITS(31, 0)
120 #define HW_DIGCTL_RAMCTRL_RSVD1 __BITS(31, 12)
121 #define HW_DIGCTL_RAMCTRL_SPEED_SELECT __BITS(11, 8)
122 #define HW_DIGCTL_RAMCTRL_RSVD0 __BITS(7, 1)
133 #define HW_DIGCTL_RAMREPAIR_RSVD1 __BITS(31, 16)
134 #define HW_DIGCTL_RAMREPAIR_ADDR __BITS(15, 0
[all...] |
| imx23_powerreg.h | 50 #define HW_POWER_CTRL_RSRVD2 __BITS(29, 28)
52 #define HW_POWER_CTRL_RSRVD1 __BITS(26, 25)
87 #define HW_POWER_5VCTRL_RSRVD6 __BITS(31, 30)
88 #define HW_POWER_5VCTRL_VBUSDROOP_TRSH __BITS(29, 28)
90 #define HW_POWER_5VCTRL_HEADROOM_ADJ __BITS(26, 24)
91 #define HW_POWER_5VCTRL_RSRVD4 __BITS(23, 21)
93 #define HW_POWER_5VCTRL_RSRVD3 __BITS(19, 18)
94 #define HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT __BITS(17, 12)
96 #define HW_POWER_5VCTRL_VBUSVALID_TRSH __BITS(10, 8)
114 #define HW_POWER_MINPWR_RSRVD1 __BITS(31, 15
[all...] |
| imx23_timrotreg.h | 55 #define HW_TIMROT_ROTCTRL_STATE __BITS(24, 22)
56 #define HW_TIMROT_ROTCTRL_DIVIDER __BITS(21, 16)
57 #define HW_TIMROT_ROTCTRL_RSRVD3 __BITS(15, 13)
59 #define HW_TIMROT_ROTCTRL_OVERSAMPLE __BITS(11, 10)
63 #define HW_TIMROT_ROTCTRL_SELECT_B __BITS(6, 4)
65 #define HW_TIMROT_ROTCTRL_SELECT_A __BITS(2, 0)
72 #define HW_TIMROT_ROTCOUNT_RSRVD1 __BITS(31, 16)
73 #define HW_TIMROT_ROTCOUNT_UPDOWN __BITS(15, 0)
83 #define HW_TIMROT_TIMCTRL0_RSRVD2 __BITS(31, 16)
86 #define HW_TIMROT_TIMCTRL0_RSRVD1 __BITS(13, 9
[all...] |
| imx23_digfiltreg.h | 56 #define HW_AUDIOIN_CTRL_RSRVD3 __BITS(29, 21)
57 #define HW_AUDIOIN_CTRL_DMAWAIT_COUNT __BITS(20, 16)
58 #define HW_AUDIOIN_CTRL_RSRVD1 __BITS(15, 11)
80 #define HW_AUDIOOUT_CTRL_RSRVD4 __BITS(29, 21)
81 #define HW_AUDIOOUT_CTRL_DMAWAIT_COUNT __BITS(20, 16)
86 #define HW_AUDIOOUT_CTRL_RSRVD2 __BITS(11, 10)
87 #define HW_AUDIOOUT_CTRL_SS3D_EFFECT __BITS(9, 8)
106 #define HW_AUDIOOUT_STAT_RSRVD1 __BITS(30, 0)
117 #define HW_AUDIOOUT_DACSRR_BASEMULT __BITS(30, 28)
119 #define HW_AUDIOOUT_DACSRR_SRC_HOLD __BITS(26, 24
[all...] |
| imx23_usbphyreg.h | 48 #define HW_USBPHY_PWD_RSVD2 __BITS(31, 21)
53 #define HW_USBPHY_PWD_RSVD1 __BITS(16, 13)
57 #define HW_USBPHY_PWD_RSVD0 __BITS(9, 0)
67 #define HW_USBPHY_TX_RSVD5 __BITS(31, 29)
68 #define HW_USBPHY_TX_USBPHY_TX_EDGECTRL __BITS(28, 26)
71 #define HW_USBPHY_TX_RSVD4 __BITS(23, 22)
74 #define HW_USBPHY_TX_TXCAL45DP __BITS(19, 16)
75 #define HW_USBPHY_TX_RSVD2 __BITS(15, 14)
78 #define HW_USBPHY_TX_TXCAL45DN __BITS(11, 8)
79 #define HW_USBPHY_TX_RSVD0 __BITS(7, 3
[all...] |
| /src/sys/arch/evbppc/wii/dev/ |
| vireg.h | 39 #define VI_VTR_ACV __BITS(13,4)
40 #define VI_VTR_EQU __BITS(3,0)
44 #define VI_DCR_FMT __BITS(9,8)
49 #define VI_DCR_LE1 __BITS(7,6)
50 #define VI_DCR_LE0 __BITS(5,4)
58 #define VI_HTR0_HCS __BITS(30,24)
59 #define VI_HTR0_HCE __BITS(22,16)
60 #define VI_HTR0_HLW __BITS(8,0)
64 #define VI_HTR1_HBS __BITS(26,17)
65 #define VI_HTR1_HBE __BITS(16,7
[all...] |
| /src/sys/arch/arm/rockchip/ |
| rk3588_iomux.c | 85 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(3,0) },
86 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(7,4) },
87 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(11,8) },
88 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(15,12) },
89 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(3,0) },
90 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(7,4) },
91 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(11,8) },
92 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(15,12) },
94 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(3,0) },
95 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(7,4) }
[all...] |
| /src/sys/arch/arm/nxp/ |
| imx6_ccmreg.h | 68 #define CCM_CCR_REG_BYPASS_COUNT __BITS(26, 21)
69 #define CCM_CCR_WB_COUNT __BITS(18, 16)
71 #define CCM_CCR_OSCNT __BITS(7, 0)
87 #define CCM_CACRR_ARM_PODF __BITS(2, 0)
90 #define CCM_CBCDR_PERIPH_CLK2_PODF __BITS(29, 27)
95 #define CCM_CBCDR_MMDC_CH0_AXI_PODF __BITS(21, 19)
96 #define CCM_CBCDR_AXI_PODF __BITS(18, 16)
97 #define CCM_CBCDR_AHB_PODF __BITS(12, 10)
98 #define CCM_CBCDR_IPG_PODF __BITS(9, 8)
100 #define CCM_CBCDR_AXI_SEL __BITS(7, 6
[all...] |
| /src/sys/arch/arm/amlogic/ |
| meson_vpureg.h | 58 #define VIU_OSD_CTRL_STAT_GLOBAL_ALPHA __BITS(20,12)
64 #define VIU_OSD_TCOLOR_R __BITS(31,24)
65 #define VIU_OSD_TCOLOR_G __BITS(23,16)
66 #define VIU_OSD_TCOLOR_B __BITS(15,8)
67 #define VIU_OSD_TCOLOR_A __BITS(7,0)
69 #define VIU_OSD_BLK_CFG_W0_TBL_ADDR __BITS(23,16)
72 #define VIU_OSD_BLK_CFG_W0_INTERP_CTRL __BITS(13,12)
73 #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE __BITS(11,8)
83 #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX __BITS(5,2)
93 #define VIU_OSD_BLK_CFG_W1_X_END __BITS(28,16
[all...] |
| meson_sdhcreg.h | 48 #define SD_SEND_TOTAL_PACK __BITS(31,16)
56 #define SD_SEND_COMMAND_INDEX __BITS(5,0)
58 #define SD_CNTL_TX_ENDIAN_CTRL __BITS(31,29)
61 #define SD_CNTL_RX_ENDIAN_CTRL __BITS(26,24)
62 #define SD_CNTL_RX_PERIOD __BITS(23,20)
63 #define SD_CNTL_RX_TIMEOUT __BITS(19,13)
64 #define SD_CNTL_PACK_LEN __BITS(12,4)
67 #define SD_CNTL_DAT_TYPE __BITS(1,0)
69 #define SD_STAT_DAT_HI __BITS(23,20)
70 #define SD_STAT_TXFIFO_COUNT __BITS(19,13
[all...] |
| meson_canvasreg.h | 38 #define DC_CAV_LUT_DATAL_FBADDR __BITS(28,0)
39 #define DC_CAV_LUT_DATAL_WIDTH_L __BITS(31,29)
41 #define DC_CAV_LUT_DATAH_BLKMODE __BITS(25,24)
47 #define DC_CAV_LUT_DATAH_HEIGHT __BITS(21,9)
48 #define DC_CAV_LUT_DATAH_WIDTH_H __BITS(8,0)
52 #define DC_CAV_LUT_ADDR_INDEX __BITS(2,0)
|
| meson_sdioreg.h | 43 #define SDIO_SEND_COMMAND_INDEX __BITS(7,0)
44 #define SDIO_SEND_RESPONSE_BITS __BITS(15,8)
51 #define SDIO_SEND_REPEAT_PACKAGE __BITS(31,24)
53 #define SDIO_CONF_COMMAND_CLK_DIV __BITS(9,0)
56 #define SDIO_CONF_COMMAND_ARG_BITS __BITS(17,12)
60 #define SDIO_CONF_M_ENDIAN __BITS(22,21)
61 #define SDIO_CONF_WRITE_NWR __BITS(28,23)
62 #define SDIO_CONF_WRITE_CRC_OK_STATUS __BITS(31,29)
64 #define SDIO_IRQS_STATUS __BITS(3,0)
77 #define SDIO_IRQS_TIMING_OUT_COUNT __BITS(31,19
[all...] |
| meson_rtcreg.h | 38 #define AO_RTC_REG0_STATIC_REG_LSB __BITS(31,24)
43 #define AO_RTC_REG0_UNUSED_19_18 __BITS(19,18)
47 #define AO_RTC_REG0_UNUSED_10_8 __BITS(10,8)
56 #define AO_RTC_REG1_UNUSED_31_16 __BITS(31,16)
57 #define AO_RTC_REG1_RESERVED __BITS(15,12)
58 #define AO_RTC_REG1_UNUSED_11_4 __BITS(11,4)
64 #define AO_RTC_REG2_OSC_CLK_COUNT __BITS(31,0)
66 #define AO_RTC_REG3_UNUSED_31_30 __BITS(31,30)
69 #define AO_RTC_REG3_AUTO_TB_SEL __BITS(27,26)
70 #define AO_RTC_REG3_FILTER_SEL __BITS(25,23
[all...] |
| /src/sys/arch/arm/nvidia/ |
| tegra_ahcisatareg.h | 34 #define TEGRA_SATA_FPCI_BAR_START __BITS(31,4)
55 #define TEGRA_T_SATA0_CFG9_BASE_ADDRESS __BITS(31,13)
67 #define TEGRA_T_SATA0_NVOOB_COMMA_CNT __BITS(30,28)
68 #define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH __BITS(27,26)
69 #define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE __BITS(25,24)
80 #define TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW __BITS(26,18)
89 #define TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE __BITS(31,16)
90 #define TEGRA_T_SATA0_BKDOOR_CC_PROG_IF __BITS(15,8)
105 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_DRV_CNTL __BITS(27,24)
106 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_PRE __BITS(23,20
[all...] |
| tegra_socthermreg.h | 38 #define SOC_THERM_TSENSOR_CONFIG0_TALL __BITS(27,8)
48 #define SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT __BITS(29,24)
49 #define SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN __BITS(20,15)
50 #define SOC_THERM_TSENSOR_CONFIG1_TSAMPLE __BITS(9,0)
53 #define SOC_THERM_TSENSOR_CONFIG2_THERM_A __BITS(31,16)
54 #define SOC_THERM_TSENSOR_CONFIG2_THERM_B __BITS(15,0)
58 #define SOC_THERM_TSENSOR_STATUS0_CAPTURE __BITS(15,0)
62 #define SOC_THERM_TSENSOR_STATUS1_TEMP __BITS(15,0)
65 #define SOC_THERM_TSENSOR_STATUS2_TEMP_MAX __BITS(31,16)
66 #define SOC_THERM_TSENSOR_STATUS2_TEMP_MIN __BITS(15,0
[all...] |
| tegra_usbreg.h | 33 #define TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES __BITS(21,16)
37 #define TEGRA_EHCI_ICUSB_CTRL_VDD1 __BITS(2,0)
40 #define TEGRA_EHCI_HOSTPC1_DEVLC_PTS __BITS(31,29)
46 #define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD __BITS(26,25)
53 #define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMX __BITS(21,20)
54 #define TEGRA_EHCI_HOSTPC1_DEVLC_H_EPLPM __BITS(19,16)
55 #define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMFRM __BITS(15,12)
58 #define TEGRA_EHCI_HOSTPC1_DEVLC_BA __BITS(11,1)
61 #define TEGRA_EHCI_USBMODE_CM __BITS(1,0)
88 #define TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB __BITS(31,25
[all...] |
| /src/sys/dev/ic/ |
| sa2400reg.h | 37 #define SA2400_TWI_DATA_MASK __BITS(31,8)
39 #define SA2400_TWI_ADDR_MASK __BITS(6,0)
49 #define SA2400_SYNA_NF_MASK __BITS(20,18) /* fractional increment value,
52 #define SA2400_SYNA_N_MASK __BITS(17,2) /* main divider division ratio,
57 #define SA2400_SYNB_R_MASK __BITS(21,12) /* reference divider ratio,
60 #define SA2400_SYNB_L_MASK __BITS(11,10) /* lock detect mode */
72 #define SA2400_SYNB_FC_MASK __BITS(7,0) /* fractional compensation
78 #define SA2400_SYNC_CP_MASK __BITS(7,6) /* charge pump current
86 #define SA2400_SYNC_SM_MASK __BITS(5,3) /* comparison divider select,
93 #define SA2400_SYND_ZERO1_MASK __BITS(21,17) /* always 0 *
[all...] |
| al2210reg.h | 49 #define AL2210_TWI_DATA_MASK __BITS(23, 4)
50 #define AL2210_TWI_ADDR_MASK __BITS(3, 0)
60 #define AL2210_CHANNEL_B_MASK __BITS(10, 5) /* Counter B */
75 #define AL2210_CHANNEL_A_MASK __BITS(4, 0) /* Counter A */
92 #define AL2210_SYNTHESIZER_R_MASK __BITS(4, 0) /* Reference
97 #define AL2210_RECEIVER_AGCDET_P_MASK __BITS(16, 15)
103 #define AL2210_RECEIVER_AGCDET_N_MASK __BITS(14, 13)
111 #define AL2210_RECEIVER_BW_SEL_MASK __BITS(4, 2)
126 #define AL2210_TRANSMITTER_PABIAS2_MASK __BITS(7, 4)
131 #define AL2210_TRANSMITTER_PABIAS1_MASK __BITS(3, 0
[all...] |
| si4136reg.h | 37 #define SI4126_TWI_DATA_MASK __BITS(21, 4)
38 #define SI4126_TWI_ADDR_MASK __BITS(3, 0)
44 #define SI4126_MAIN_AUXSEL_MASK __BITS(13, 12) /* aux. output pin function */
52 #define SI4126_MAIN_IFDIV_MASK __BITS(11, 10) /* IFOUT = IFVCO
69 #define SI4126_GAIN_KPI_MASK __BITS(5, 4) /* IF phase detector gain */
70 #define SI4126_GAIN_KP2_MASK __BITS(3, 2) /* RF2 phase detector gain */
71 #define SI4126_GAIN_KP1_MASK __BITS(1, 0) /* RF1 phase detector gain */
|
| /src/sys/arch/mips/cavium/dev/ |
| octeon_faureg.h | 43 #define POW_LOAD_INCVAL __BITS(35,14)
45 /* reserved __BiTS(12,11) */
46 #define POW_LOAD_REG __BITS(10,0)
53 #define POW_IOBDMA_SIZE __BITS(12,11)
57 /* reserved __BiTS(35,14) */
59 /* reserved __BiTS(12,11) */
60 #define POW_STORE_REG __BITS(10,0)
|
| /src/sys/arch/arm/broadcom/ |
| bcm2838_pcie.h | 37 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1 __BITS(0,1)
38 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2 __BITS(2,3)
39 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3 __BITS(4,5)
42 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE __BITS(0,23)
45 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT __BITS(10,11)
50 #define PCIE_RC_DL_MDIO_DATA __BITS(0,30)
51 #define PCIE_RC_DL_MDIO_PORT __BITS(16,19)
52 #define PCIE_RC_DL_MDIO_REGAD __BITS(0,15)
53 #define PCIE_RC_DL_MDIO_CMD __BITS(20,31)
61 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE __BITS(20,21
[all...] |
| /src/sys/arch/arm/cortex/ |
| gic_reg.h | 91 #define GICC_PMR_PRIORITY __BITS(7,0)
101 #define GICC_IAR_CPUID __BITS(12,10)
102 #define GICC_IAR_IRQ __BITS(9,0)
106 #define GICC_EOIR_CPUID __BITS(12,10)
107 #define GICC_EOIR_InterruptID __BITS(9,0)
109 #define GICC_HPPIR_CPUID __BITS(12,10)
110 #define GICC_HPPIR_PendIntID __BITS(9,0)
112 #define GICC_IIDR_ProductID __BITS(31,20)
113 #define GICC_IIDR_ArchVersion __BITS(19,16)
114 #define GICC_IIDR_Revision __BITS(15,12
[all...] |
