Searched refs:OUT_BATCH (Results 1 - 25 of 149) sorted by relevance

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/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_3d.c40 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
41 OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
45 OUT_BATCH(0); /* write address */
46 OUT_BATCH(0); /* write data */
48 OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
50 OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | ((ivb ? 4 : 3) - 2));
51 OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
53 OUT_BATCH(0);
55 OUT_BATCH(0);
57 OUT_BATCH(GEN6_3DSTATE_SAMPLE_MAS
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H A Di915_3d.c45 OUT_BATCH(_3DSTATE_AA_CMD |
51 OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
59 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
60 OUT_BATCH(0);
62 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
63 OUT_BATCH(0);
65 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
66 OUT_BATCH(0);
69 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
77 OUT_BATCH(_3DSTATE_RASTER_RULES_CM
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H A Di830_3d.c45 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
46 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
47 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
48 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
50 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
51 OUT_BATCH(0);
53 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
54 OUT_BATCH(0);
56 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
57 OUT_BATCH(
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H A Dintel_batchbuffer.c158 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
159 OUT_BATCH(BRW_PIPE_CONTROL_CS_STALL |
161 OUT_BATCH(0); /* address */
162 OUT_BATCH(0); /* write data */
164 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
165 OUT_BATCH(BRW_PIPE_CONTROL_WRITE_QWORD);
168 OUT_BATCH(0); /* write data */
171 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
172 OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
175 OUT_BATCH(
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H A Di915_video.c119 OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
120 OUT_BATCH(DRAW_DITHER_OFS_X(pixmap->drawable.x & 3) |
122 OUT_BATCH(0x00000000); /* ymin, xmin */
124 OUT_BATCH((target->drawable.width - 1) |
126 OUT_BATCH(0x00000000); /* yorigin, xorigin */
128 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
130 OUT_BATCH(S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) |
141 OUT_BATCH(s5); /* S5 - enable bits */
142 OUT_BATCH((2 << S6_DEPTH_TEST_FUNC_SHIFT) |
147 OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CM
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/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_3d.c40 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
41 OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
45 OUT_BATCH(0); /* write address */
46 OUT_BATCH(0); /* write data */
48 OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
50 OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | ((ivb ? 4 : 3) - 2));
51 OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
53 OUT_BATCH(0);
55 OUT_BATCH(0);
57 OUT_BATCH(GEN6_3DSTATE_SAMPLE_MAS
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H A Di915_3d.c45 OUT_BATCH(_3DSTATE_AA_CMD |
51 OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
59 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
60 OUT_BATCH(0);
62 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
63 OUT_BATCH(0);
65 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
66 OUT_BATCH(0);
69 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
77 OUT_BATCH(_3DSTATE_RASTER_RULES_CM
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H A Di830_3d.c45 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
46 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
47 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
48 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
50 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
51 OUT_BATCH(0);
53 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
54 OUT_BATCH(0);
56 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
57 OUT_BATCH(
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H A Di915_video.c119 OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
120 OUT_BATCH(DRAW_DITHER_OFS_X(pixmap->drawable.x & 3) |
122 OUT_BATCH(0x00000000); /* ymin, xmin */
124 OUT_BATCH((target->drawable.width - 1) |
126 OUT_BATCH(0x00000000); /* yorigin, xorigin */
128 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
130 OUT_BATCH(S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) |
141 OUT_BATCH(s5); /* S5 - enable bits */
142 OUT_BATCH((2 << S6_DEPTH_TEST_FUNC_SHIFT) |
147 OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CM
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H A Dintel_batchbuffer.c158 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
159 OUT_BATCH(BRW_PIPE_CONTROL_CS_STALL |
161 OUT_BATCH(0); /* address */
162 OUT_BATCH(0); /* write data */
164 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
165 OUT_BATCH(BRW_PIPE_CONTROL_WRITE_QWORD);
168 OUT_BATCH(0); /* write data */
171 OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
172 OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
175 OUT_BATCH(
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/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dgfx8_multisample_state.c37 OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2));
40 OUT_BATCH(brw_multisample_positions_16x[0]); /* positions 3, 2, 1, 0 */
41 OUT_BATCH(brw_multisample_positions_16x[1]); /* positions 7, 6, 5, 4 */
42 OUT_BATCH(brw_multisample_positions_16x[2]); /* positions 11, 10, 9, 8 */
43 OUT_BATCH(brw_multisample_positions_16x[3]); /* positions 15, 14, 13, 12 */
46 OUT_BATCH(brw_multisample_positions_8x[1]); /* sample positions 7654 */
47 OUT_BATCH(brw_multisample_positions_8x[0]); /* sample positions 3210 */
50 OUT_BATCH(brw_multisample_positions_4x);
53 OUT_BATCH(brw_multisample_positions_1x_2x);
H A Dgfx6_sampler_state.c37 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
42 OUT_BATCH(brw->vs.base.sampler_offset); /* VS */
43 OUT_BATCH(brw->gs.base.sampler_offset); /* GS */
44 OUT_BATCH(brw->wm.base.sampler_offset);
H A Dhsw_sol.c105 OUT_BATCH(HSW_MI_MATH | (9 - 2));
107 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2));
108 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1));
109 OUT_BATCH(MI_MATH_ALU0(SUB));
110 OUT_BATCH(MI_MATH_ALU2(STORE, R1, ACCU));
112 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0));
113 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1));
114 OUT_BATCH(MI_MATH_ALU0(ADD));
115 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
128 OUT_BATCH(HSW_MI_MAT
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H A Dbrw_misc_state.c62 OUT_BATCH(MI_FLUSH);
67 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
72 OUT_BATCH(0);
293 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
294 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch_B - 1 : 0) |
303 OUT_BATCH(0);
306 OUT_BATCH(((width + tile_x - 1) << 6) |
308 OUT_BATCH(0);
311 OUT_BATCH(tile_x | (tile_y << 16));
316 OUT_BATCH(
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/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.c43 OUT_BATCH(_3DSTATE_AA_CMD |
50 OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
56 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
57 OUT_BATCH(0);
59 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
60 OUT_BATCH(0);
62 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
63 OUT_BATCH(0);
66 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
76 OUT_BATCH(_3DSTATE_RASTER_RULES_CM
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H A Di830_3d.c44 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
45 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
46 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
47 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
49 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
50 OUT_BATCH(0);
52 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
53 OUT_BATCH(0);
55 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
56 OUT_BATCH(
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H A Di915_video.c95 OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
96 OUT_BATCH(0x00000000);
99 OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
100 OUT_BATCH(DRAW_DITHER_OFS_X(pPixmap->drawable.x & 3) |
102 OUT_BATCH(0x00000000); /* ymin, xmin */
103 OUT_BATCH((pPixmap->drawable.width - 1) |
105 OUT_BATCH(0x00000000); /* yorigin, xorigin */
106 OUT_BATCH(MI_NOOP);
108 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
110 OUT_BATCH(S2_TEXCOORD_FM
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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dgen8_multisample_state.c83 OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2));
86 OUT_BATCH(brw_multisample_positions_16x[0]); /* positions 3, 2, 1, 0 */
87 OUT_BATCH(brw_multisample_positions_16x[1]); /* positions 7, 6, 5, 4 */
88 OUT_BATCH(brw_multisample_positions_16x[2]); /* positions 11, 10, 9, 8 */
89 OUT_BATCH(brw_multisample_positions_16x[3]); /* positions 15, 14, 13, 12 */
92 OUT_BATCH(brw_multisample_positions_8x[1]); /* sample positions 7654 */
93 OUT_BATCH(brw_multisample_positions_8x[0]); /* sample positions 3210 */
96 OUT_BATCH(brw_multisample_positions_4x);
99 OUT_BATCH(brw_multisample_positions_1x_2x);
H A Dgen6_sampler_state.c37 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
42 OUT_BATCH(brw->vs.base.sampler_offset); /* VS */
43 OUT_BATCH(brw->gs.base.sampler_offset); /* GS */
44 OUT_BATCH(brw->wm.base.sampler_offset);
H A Dhsw_sol.c105 OUT_BATCH(HSW_MI_MATH | (9 - 2));
107 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2));
108 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1));
109 OUT_BATCH(MI_MATH_ALU0(SUB));
110 OUT_BATCH(MI_MATH_ALU2(STORE, R1, ACCU));
112 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0));
113 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1));
114 OUT_BATCH(MI_MATH_ALU0(ADD));
115 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
128 OUT_BATCH(HSW_MI_MAT
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H A Dbrw_misc_state.c62 OUT_BATCH(MI_FLUSH);
67 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
72 OUT_BATCH(0);
293 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
294 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch_B - 1 : 0) |
303 OUT_BATCH(0);
306 OUT_BATCH(((width + tile_x - 1) << 6) |
308 OUT_BATCH(0);
311 OUT_BATCH(tile_x | (tile_y << 16));
316 OUT_BATCH(
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_blit.c78 OUT_BATCH(CMD);
79 OUT_BATCH(BR13);
80 OUT_BATCH((y << 16) | x);
81 OUT_BATCH(((y + h) << 16) | (x + w));
83 OUT_BATCH(color);
150 OUT_BATCH(CMD);
151 OUT_BATCH(BR13);
152 OUT_BATCH((dst_y << 16) | dst_x);
153 OUT_BATCH((dst_y2 << 16) | dst_x2);
155 OUT_BATCH((src_
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H A Di915_clear.c133 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
135 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
136 OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT);
138 OUT_BATCH(clear_color);
139 OUT_BATCH(clear_depth);
141 OUT_BATCH(clear_color8888);
143 OUT_BATCH(clear_stencil);
145 OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5);
153 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
154 OUT_BATCH((clear_param
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_blit.c68 OUT_BATCH(CMD);
69 OUT_BATCH(BR13);
70 OUT_BATCH((y << 16) | x);
71 OUT_BATCH(((y + h) << 16) | (x + w));
73 OUT_BATCH(color);
131 OUT_BATCH(CMD);
132 OUT_BATCH(BR13);
133 OUT_BATCH((dst_y << 16) | dst_x);
134 OUT_BATCH((dst_y2 << 16) | dst_x2);
136 OUT_BATCH((src_
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H A Di915_clear.c134 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
136 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
137 OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT);
139 OUT_BATCH(clear_color);
140 OUT_BATCH(clear_depth);
142 OUT_BATCH(clear_color8888);
144 OUT_BATCH(clear_stencil);
146 OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5);
154 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
155 OUT_BATCH((clear_param
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