Searched refs:S6_CBUF_DST_BLEND_FACT_SHIFT (Results 1 - 24 of 24) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Dintel_reg.h178 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
H A Di915_reg.h321 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
H A Di915_state.c259 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Dintel_reg.h178 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
H A Di915_reg.h321 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
H A Di915_state.c259 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_reg.h431 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
442 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_reg.h409 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
418 #define DST_BLND_FACT(f) ((f) << S6_CBUF_DST_BLEND_FACT_SHIFT)
H A Di915_state.c113 uint32_t dst = (lis6 >> S6_CBUF_DST_BLEND_FACT_SHIFT) & BLENDFACT_MASK;
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_video.c126 (1 << S6_CBUF_DST_BLEND_FACT_SHIFT) | S6_COLOR_WRITE_ENABLE |
H A Di915_reg.h451 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
H A Di915_render.c136 (dblend << S6_CBUF_DST_BLEND_FACT_SHIFT);
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_video.c144 (1 << S6_CBUF_DST_BLEND_FACT_SHIFT) |
H A Di915_reg.h434 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
H A Di915_render.c141 (dblend << S6_CBUF_DST_BLEND_FACT_SHIFT);
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_video.c144 (1 << S6_CBUF_DST_BLEND_FACT_SHIFT) |
H A Di915_reg.h434 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
H A Di915_render.c141 (dblend << S6_CBUF_DST_BLEND_FACT_SHIFT);
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_reg.h434 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_reg.h434 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h437 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
H A Dgen3_render.c99 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT)
195 dblend << S6_CBUF_DST_BLEND_FACT_SHIFT);
5144 (1 << S6_CBUF_DST_BLEND_FACT_SHIFT) |
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h437 #define S6_CBUF_DST_BLEND_FACT_SHIFT 4 macro
H A Dgen3_render.c99 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT)
195 dblend << S6_CBUF_DST_BLEND_FACT_SHIFT);
5074 (1 << S6_CBUF_DST_BLEND_FACT_SHIFT) |

Completed in 52 milliseconds