Searched refs:dispatch_mode (Results 1 - 25 of 30) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dtest_vec4_dead_code_eliminate.cpp51 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
H A Dbrw_vec4_gs_visitor.cpp133 prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
855 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
880 prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
941 prog_data->base.dispatch_mode = DISPATCH_MODE_4X1_SINGLE;
943 prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_INSTANCE;
H A Dtest_vec4_copy_propagation.cpp53 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
H A Dtest_vec4_register_coalesce.cpp56 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
H A Dbrw_vec4.cpp2165 enum shader_dispatch_mode dispatch_mode)
2171 return dispatch_mode != DISPATCH_MODE_4X2_DUAL_OBJECT;
2185 enum shader_dispatch_mode dispatch_mode,
2227 stage_uses_interleaved_attributes(stage, dispatch_mode))
2281 get_lowered_simd_width(devinfo, prog_data->dispatch_mode, stage, inst);
2339 prog_data->dispatch_mode);
2437 (stage_uses_interleaved_attributes(stage, prog_data->dispatch_mode) &&
2962 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
2993 prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
2164 stage_uses_interleaved_attributes(unsigned stage,enum shader_dispatch_mode dispatch_mode) argument
2184 get_lowered_simd_width(const struct gen_device_info * devinfo,enum shader_dispatch_mode dispatch_mode,unsigned stage,const vec4_instruction * inst) argument
H A Dbrw_vec4_copy_propagation.cpp478 prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
H A Dbrw_vec4_tcs.cpp472 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
H A Dbrw_compiler.h1054 enum shader_dispatch_mode dispatch_mode; member in struct:brw_vue_prog_data
H A Dbrw_shader.cpp1332 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
H A Dtest_vec4_cmod_propagation.cpp55 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dtest_vec4_dead_code_eliminate.cpp53 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
H A Dbrw_vec4_gs_visitor.cpp134 prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
826 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
857 prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
922 prog_data->base.dispatch_mode = DISPATCH_MODE_4X1_SINGLE;
924 prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_INSTANCE;
H A Dtest_vec4_copy_propagation.cpp53 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
H A Dbrw_vec4_tcs.cpp410 vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH;
415 vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_SINGLE_PATCH;
H A Dtest_vec4_register_coalesce.cpp56 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
H A Dbrw_vec4.cpp2196 enum shader_dispatch_mode dispatch_mode)
2202 return dispatch_mode != DISPATCH_MODE_4X2_DUAL_OBJECT;
2216 enum shader_dispatch_mode dispatch_mode,
2258 stage_uses_interleaved_attributes(stage, dispatch_mode))
2312 get_lowered_simd_width(devinfo, prog_data->dispatch_mode, stage, inst);
2370 prog_data->dispatch_mode);
2468 (stage_uses_interleaved_attributes(stage, prog_data->dispatch_mode) &&
2987 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
3019 prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
2195 stage_uses_interleaved_attributes(unsigned stage,enum shader_dispatch_mode dispatch_mode) argument
2215 get_lowered_simd_width(const struct intel_device_info * devinfo,enum shader_dispatch_mode dispatch_mode,unsigned stage,const vec4_instruction * inst) argument
H A Dbrw_vec4_copy_propagation.cpp464 prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
H A Dbrw_compiler.h1294 enum shader_dispatch_mode dispatch_mode; member in struct:brw_vue_prog_data
H A Dbrw_shader.cpp1434 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_pipeline.c1333 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
1489 tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
1493 assert(tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
1527 gs.DispatchMode = gs_prog_data->base.dispatch_mode;
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_pipeline.c1779 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
1912 hs.DispatchMode = tcs_prog_data->base.dispatch_mode;
1966 tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
1970 assert(tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
2009 gs.DispatchMode = gs_prog_data->base.dispatch_mode;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c2132 assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
2133 vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
2135 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
2201 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
2617 gs.DispatchMode = vue_prog_data->dispatch_mode;
4038 hs.DispatchMode = vue_prog_data->dispatch_mode;
4073 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
4083 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8)
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c2149 assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
2150 vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
2152 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
2218 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
2719 gs.DispatchMode = vue_prog_data->dispatch_mode;
4146 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
4156 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8)
/xsrc/external/mit/MesaLib.old/dist/src/intel/blorp/
H A Dblorp_genX_exec.h621 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
640 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
/xsrc/external/mit/MesaLib/dist/src/intel/blorp/
H A Dblorp_genX_exec.h686 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
705 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;

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