Searched refs:ENABLE_STENCIL_TEST_MASK (Results 1 - 25 of 32) sorted by relevance

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/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.c88 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
H A Di830_3d.c165 ENABLE_STENCIL_TEST_MASK |
H A Di830_reg.h517 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
H A Di915_reg.h453 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.c88 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
H A Di830_3d.c165 ENABLE_STENCIL_TEST_MASK |
H A Di830_reg.h511 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
H A Di915_reg.h453 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.c89 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
H A Di830_3d.c176 ENABLE_STENCIL_TEST_MASK |
H A Di830_reg.h449 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di830_reg.h396 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
H A Di915_reg.h341 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
H A Di830_state.c65 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
1018 ENABLE_STENCIL_TEST_MASK |
H A Di915_state.c110 ENABLE_STENCIL_TEST_MASK |
946 ENABLE_STENCIL_TEST_MASK |
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di830_reg.h396 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
H A Di915_reg.h341 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
H A Di830_state.c65 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
1018 ENABLE_STENCIL_TEST_MASK |
H A Di915_state.c110 ENABLE_STENCIL_TEST_MASK |
946 ENABLE_STENCIL_TEST_MASK |
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen2_render.h440 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di830_reg.h511 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
H A Di915_reg.h453 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen2_render.h440 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di830_reg.h511 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro
H A Di915_reg.h453 #define ENABLE_STENCIL_TEST_MASK (1<<17) macro

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